This application is based upon and claims the benefit of priority from the prior Japanese patent application No. 2002-309750, filed on Oct. 24, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an oversampling modulator device which is used for digital-to-analog conversion and analog-to-digital conversion, and more particularly to an oversampling modulator device which is used to suppress the quantizing error in a delta modulator, a sigma-delta modulator or a multi-stage error shaping modulator.
2. Description of the Related Art
Digital-to-analog conversion is the process of converting digital codes into a range of analog signal levels. Analog-to-digital conversion is the process of converting a range of analog signal levels into digital codes. According to the Nyquist sampling criterion, A/D converters which use a sampling frequency that is slightly more than twice the highest frequency in the analog signal allow the original information of the analog signal to be transmitted and restored without loss.
Suppose that the highest frequency in the analog signal is indicated by xe2x80x9cfaxe2x80x9d, the sampling frequency is indicated by xe2x80x9cfbxe2x80x9d, and the number of bits (resolution) in the digital code is indicated by xe2x80x9cnxe2x80x9d (fa, fb, and n are positive integers). The maximum xe2x80x9cS/N_MAXxe2x80x9d of the signal-to-noise ratio S/N in the analog-to-digital conversion is represented by the following formula:
S/N_MAX=(3/2)xc3x9722nxc3x97(fa/2fb)
As is apparent from the above formula, if the bit number xe2x80x9cnxe2x80x9d is raised by one, the signal-to-noise ratio S/N is improved by 6 dB. If the sampling frequency xe2x80x9cfbxe2x80x9d is doubled, the signal-to-noise ratio S/N is improved by 3 dB. Thus, in order to raise the accuracy of conversion (or to lesson the quantizing noise), it is necessary to increase the number of bits or to raise the sampling frequency.
Moreover, using a sigma-delta modulator makes it possible that the quantizing noise is made large at the high frequency side and made small at the low frequency side. Hence, if the quantizing noise becomes low in the vicinity of the highest frequency in the analog signal, the signal can be restored with a high level of accuracy.
FIG. 1 shows an example of a conventional oversampling modulator device.
The conventional oversampling modulator device in FIG. 1 includes an adder 21, a subtractor 22, a quantizer 23, a delay element 24, a delay element 25, and a decoder 26.
The adder 21 outputs a signal 202 indicating a sum of a 10-bit input signal 201 and a 10-bit return signal 204. The subtractor 22 outputs a difference signal 203 indicating a difference between a 10-bit return signal 206 and the 11-bit output signal 202 from the adder 21. The quantizer 23 performs a quantization process of the output signal 203 of the subtractor 22, and outputs a 10-bit quantization signal 205 indicating the quantization result. The quantization signal 205 is sent to a decoder 26. The decoder 26 performs the decoding process of the quantization signal 205 and outputs a 3-bit output signal 207, indicating the decoding result, to a subsequent-stage external device (not shown).
The output signal 203 of the subtractor 22 is sent to the delay element 24, and the delay of one clock is added to the signal 203 at the delay element 24. The delay element 24 outputs the one-clock delayed signal to the adder 21 as the 10-bit return signal 204.
Moreover, the quantization signal 205 outputted by the quantizer 23 is sent to the delay element 25, and the delay of one clock is added to the signal 205 at the delay element 25. The delay element 25 outputs the one-clock delayed signal to the subtractor 22 as the 10-bit return signal 206.
FIG. 2 shows an example of a conventional quantizer in a case of setting the quantization width to 128.
The quantizer shown in FIG. 2 includes magnitude comparators 30, 31 and 32, AND gates 33 and 34, selector units 35, 36, 37 and 38, and an OR gate 39.
In the quantizer of FIG. 2, each of the magnitude comparators 30-32 has two inputs A and B and two outputs G and L, and operates as follows. When the inputs A and B of the comparator meet the condition A less than B, the output L of the comparator is set to 1 and the output G of the comparator is set to 0, and when the conditions Axe2x89xa7B are met, the output L of the comparator is set to 0 and the output G of the comparator is set to 1.
The input signal 300 corresponds to the 10-bit signal 203 in the conventional modulator device of FIG. 1. The input signal 300 is sent to each of the inputs A of the magnitude comparators 30, 31 and 32.
Suppose that the quantization width of the quantizer of FIG. 2 is set to 128 (in decimal number). The input signal 310 which is sent to the input B of the magnitude comparator 30 and one input of the selector 36 is set to 128 in decimal. The input signal 311 which is sent to the input B of magnitude comparator 31 and one input of the selector 37 is set to 256 in decimal. The input signal 312 which is sent to the input B of the magnitude comparator 32 and one input of the selector 38 is set to 384 in decimal. The input signal 313 which is sent to one input of the selector 35 is set to 0 in decimal.
The output L of the magnitude comparator 30 is connected to the other input of the selector 35 through the signal line 301. The output G of the magnitude comparator 30 and the output L of the magnitude comparator 31 are connected to the two inputs of the AND gate 33 through the signal line 302 and the signal line 303, respectively. The output G of the magnitude comparator 31 and the output L of the magnitude comparator 32 are connected to the two inputs of the AND gate 34 through the signal line 304 and the signal line 305, respectively. The output G of the magnitude comparator 32 is connected to the other input of the selector 38 through the signal line 306.
The output of the AND gate 33 is connected to the other input of the selector 36 through the signal line 307. The output of the AND gate 34 is connected to the other input of the selector 37 through the signal line 308. All of the outputs of the selectors 35, 36, 37 and 38 are connected to the inputs of the OR gate 39. Therefore, the OR gate 39 outputs the quantization signal 309 by taking the OR of the output signals which are outputted by the selector 35, 36, 37 and 38 in response to the input signal 300.
In the quantizer of FIG. 2, when the input signal 300 is indicative of a number less than 128, only the signal sent on the signal line 301 is set to 1 and all the signals sent on the signal line 306, the signal line 307 and the signal line 308 are set to 0. When the input signal 300 is indicative of a number above 128 and less than 256, the signals sent on the signal line 302 and the signal line 303 are set to 1, the signal sent on the signal line 307 is set to 1, and all the signals sent on the signal line 301, the signal line 306 and the signal line 308 are set to 0.
Moreover, when the input signal 300 is indicative of a number above 256 and less than 384, the signals sent on the signal line 304 and the signal line 305 are set to 1, the signal sent on the signal line 308 is set to 1, and all the signals sent on the signal line 301, the signal line 306 and the signal line 307 are set to 0. When the input signal 300 is indicative of a number above 384, only the signal sent on the signal line 306 is set to 1 and all the signals sent on the signal line 301, the signal line 306 and the signal line 307 are set to 0.
In the case of the above-mentioned conventional device, it is necessary to complete the addition and subtraction operations, (i.e., the operations from the processing of the input signal 201 to the processing of the output signal 205 as shown in FIG. 1) within a prescribed period of time corresponding to one clock.
In addition, Japanese Laid-Open Patent Application No. 6-13906 discloses a sigma-delta modulator for use in an oversampling D/A converter to realize a high S/N ratio, as the conventional technology related to the present invention.
For the purpose of raising the operational accuracy in the conventional oversampling modulator device, the increase in the number of operation bits of the oversampling modulator and the improvement in the speed of signal processing may be taken into consideration.
However, in the case of the conventional oversampling modulator device, it is difficult to increase the number of operation bits or to accelerate the signal processing, while satisfying the conditions that the logical operations be completed within the prescribed period of time corresponding to one clock.
Moreover, a plurality of the same operational circuits may be provided in the parallel connection, so that the parallel operation is carried out in order to raise the operational accuracy in the conventional oversampling modulator device. However, the circuit scale would be large in such a case and the chip area would be increased. There is the problem that the cost is increased, and the power dissipation is also increased.
An object of the present invention is to provide an improved oversampling modulator device in which the above-mentioned problems are eliminated.
Another object of the present invention is to provide an oversampling modulator device that uses a simple quantizer in which the quantization width is set to 2k (k: a positive integer), realizes multiple-bit signal processing and high-speed data processing, and reduces the number of the bits in the operational circuit without increasing the circuit scale.
The above-mentioned objects of the present invention are achieved by an oversampling modulator device comprising: an addition unit outputting an signal indicating a sum of an input signal and a first delayed signal, the input signal having a plurality of bits, the output signal divided into a first signal having a number of upper bits of the output signal and a second signal having the remaining bits of the output signal; a subtraction unit outputting a signal indicating a difference between the first signal from the addition unit and a second delayed signal; a first delay unit outputting the first delayed signal to the addition unit by delaying a third signal having upper bits produced by the output signal of the subtraction unit and lower bits produced by the second signal from the addition unit; a quantization unit performing quantization processing of the third signal and outputting a quantization signal having a predetermined number of bits; and a second delay unit outputting the second delayed signal to the subtraction unit by delaying the quantization signal, wherein the quantization unit selects specific bits included in the third signal and generates the quantization signal with the selected bits of the third signal.
The above-mentioned objects of the present invention are achieved by an oversampling modulator device comprising: a subtraction unit outputting an signal indicating a difference between a first signal and a first delayed signal, the first signal having a number of upper bits included in an input signal, the input signal having a plurality of bits and being divided into the first signal and a second signal; an addition unit outputting a signal indicating a sum of a third signal and a second delayed signal, the third signal having upper bits produced by the output signal of the subtraction unit and lower bits produced by the second signal having the remaining bits of the input signal; a quantization unit performing quantization processing of the output signal of the addition unit and outputting a quantization signal having a predetermined number of bits; a first delay unit outputting the first delayed signal to the subtraction unit by delaying the quantization signal from the quantization unit; and a second delay unit outputting the second delayed signal to the addition unit by delaying the output signal of the addition unit, wherein the quantization unit selects specific bits included in the output signal of the addition unit and generates the quantization signal with the selected bits of the output signal of the addition unit.
The oversampling modulator device of the present invention uses the quantization unit which has the quantization width set to 2k (k: a positive integer) and operates at high speed. According to the oversampling modulator device of the present invention, high-speed data processing and multiple-bit signal processing can be realized without increasing the circuit scale. Therefore, by using the high-speed oversampling modulator device of the present invention, it is possible to contribute to the production of integrated circuits with low cost and low power dissipation.